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Added cbmem with "local" sources

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pull/5/head
xSmurf 9 years ago
parent 3f695b0bfa
commit b711a810a6
9 changed files with 1963 additions and 0 deletions
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44
board/coreboot/packages/cbmem/Makefile
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##
## This file is part of the coreboot project.
##
## Copyright (C) 2012 The ChromiumOS Authors. All rights reserved.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc.
##
PROGRAM = cbmem
#ROOT = ../../src
CC ?= $(CROSS_COMPILE)gcc
CFLAGS ?= -Os
CFLAGS += -Wall -Werror
#CPPFLAGS += -iquote $(ROOT)/include -iquote $(ROOT)/src/arch/x86
OBJS = $(PROGRAM).o
all: $(PROGRAM)
$(PROGRAM): $(OBJS)
clean:
rm -f $(PROGRAM) *.o *~
distclean: clean
rm -f .dependencies
.dependencies:
@$(CC) $(CFLAGS) $(CPPFLAGS) -MM *.c > .dependencies
.PHONY: all clean distclean
-include .dependencies

1240
board/coreboot/packages/cbmem/cbmem.c
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113
board/coreboot/packages/cbmem/cbmem_id.h
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2009 coresystems GmbH
* Copyright (C) 2013 Google, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc.
*/
#ifndef _CBMEM_ID_H_
#define _CBMEM_ID_H_
#define CBMEM_ID_ACPI 0x41435049
#define CBMEM_ID_ACPI_GNVS 0x474e5653
#define CBMEM_ID_ACPI_GNVS_PTR 0x474e5650
#define CBMEM_ID_AGESA_RUNTIME 0x41474553
#define CBMEM_ID_AMDMCT_MEMINFO 0x494D454E
#define CBMEM_ID_CAR_GLOBALS 0xcac4e6a3
#define CBMEM_ID_CBTABLE 0x43425442
#define CBMEM_ID_CONSOLE 0x434f4e53
#define CBMEM_ID_COVERAGE 0x47434f56
#define CBMEM_ID_EHCI_DEBUG 0xe4c1deb9
#define CBMEM_ID_ELOG 0x454c4f47
#define CBMEM_ID_FREESPACE 0x46524545
#define CBMEM_ID_FSP_RESERVED_MEMORY 0x46535052
#define CBMEM_ID_FSP_RUNTIME 0x52505346
#define CBMEM_ID_GDT 0x4c474454
#define CBMEM_ID_HOB_POINTER 0x484f4221
#define CBMEM_ID_IGD_OPREGION 0x4f444749
#define CBMEM_ID_IMD_ROOT 0xff4017ff
#define CBMEM_ID_IMD_SMALL 0x53a11439
#define CBMEM_ID_MEMINFO 0x494D454D
#define CBMEM_ID_MPTABLE 0x534d5054
#define CBMEM_ID_MRCDATA 0x4d524344
#define CBMEM_ID_MTC 0xcb31d31c
#define CBMEM_ID_NONE 0x00000000
#define CBMEM_ID_PIRQ 0x49525154
#define CBMEM_ID_POWER_STATE 0x50535454
#define CBMEM_ID_RAM_OOPS 0x05430095
#define CBMEM_ID_RAMSTAGE 0x9a357a9e
#define CBMEM_ID_RAMSTAGE_CACHE 0x9a3ca54e
#define CBMEM_ID_REFCODE 0x04efc0de
#define CBMEM_ID_REFCODE_CACHE 0x4efc0de5
#define CBMEM_ID_RESUME 0x5245534d
#define CBMEM_ID_RESUME_SCRATCH 0x52455343
#define CBMEM_ID_ROMSTAGE_INFO 0x47545352
#define CBMEM_ID_ROMSTAGE_RAM_STACK 0x90357ac4
#define CBMEM_ID_ROOT 0xff4007ff
#define CBMEM_ID_SMBIOS 0x534d4254
#define CBMEM_ID_SMM_SAVE_SPACE 0x07e9acee
#define CBMEM_ID_SPINTABLE 0x59175917
#define CBMEM_ID_STAGEx_META 0x57a9e000
#define CBMEM_ID_STAGEx_CACHE 0x57a9e100
#define CBMEM_ID_TCPA_LOG 0x54435041
#define CBMEM_ID_TIMESTAMP 0x54494d45
#define CBMEM_ID_VBOOT_HANDOFF 0x780074f0
#define CBMEM_ID_VBOOT_WORKBUF 0x78007343
#define CBMEM_ID_WIFI_CALIBRATION 0x57494649
#define CBMEM_ID_TO_NAME_TABLE \
{ CBMEM_ID_ACPI, "ACPI " }, \
{ CBMEM_ID_ACPI_GNVS, "ACPI GNVS " }, \
{ CBMEM_ID_ACPI_GNVS_PTR, "GNVS PTR " }, \
{ CBMEM_ID_AGESA_RUNTIME, "AGESA RSVD " }, \
{ CBMEM_ID_AMDMCT_MEMINFO, "AMDMEM INFO" }, \
{ CBMEM_ID_CAR_GLOBALS, "CAR GLOBALS" }, \
{ CBMEM_ID_CBTABLE, "COREBOOT " }, \
{ CBMEM_ID_CONSOLE, "CONSOLE " }, \
{ CBMEM_ID_COVERAGE, "COVERAGE " }, \
{ CBMEM_ID_EHCI_DEBUG, "USBDEBUG " }, \
{ CBMEM_ID_ELOG, "ELOG " }, \
{ CBMEM_ID_FREESPACE, "FREE SPACE " }, \
{ CBMEM_ID_FSP_RESERVED_MEMORY, "FSP MEMORY " }, \
{ CBMEM_ID_FSP_RUNTIME, "FSP RUNTIME" }, \
{ CBMEM_ID_GDT, "GDT " }, \
{ CBMEM_ID_IMD_ROOT, "IMD ROOT " }, \
{ CBMEM_ID_IMD_SMALL, "IMD SMALL " }, \
{ CBMEM_ID_MEMINFO, "MEM INFO " }, \
{ CBMEM_ID_MPTABLE, "SMP TABLE " }, \
{ CBMEM_ID_MRCDATA, "MRC DATA " }, \
{ CBMEM_ID_MTC, "MTC " }, \
{ CBMEM_ID_PIRQ, "IRQ TABLE " }, \
{ CBMEM_ID_POWER_STATE, "POWER STATE" }, \
{ CBMEM_ID_RAM_OOPS, "RAMOOPS " }, \
{ CBMEM_ID_RAMSTAGE_CACHE, "RAMSTAGE $ " }, \
{ CBMEM_ID_RAMSTAGE, "RAMSTAGE " }, \
{ CBMEM_ID_REFCODE_CACHE, "REFCODE $ " }, \
{ CBMEM_ID_REFCODE, "REFCODE " }, \
{ CBMEM_ID_RESUME, "ACPI RESUME" }, \
{ CBMEM_ID_RESUME_SCRATCH, "ACPISCRATCH" }, \
{ CBMEM_ID_ROMSTAGE_INFO, "ROMSTAGE " }, \
{ CBMEM_ID_ROMSTAGE_RAM_STACK, "ROMSTG STCK" }, \
{ CBMEM_ID_ROOT, "CBMEM ROOT " }, \
{ CBMEM_ID_SMBIOS, "SMBIOS " }, \
{ CBMEM_ID_SMM_SAVE_SPACE, "SMM BACKUP " }, \
{ CBMEM_ID_SPINTABLE, "SPIN TABLE " }, \
{ CBMEM_ID_TCPA_LOG, "TCPA LOG " }, \
{ CBMEM_ID_TIMESTAMP, "TIME STAMP " }, \
{ CBMEM_ID_VBOOT_HANDOFF, "VBOOT " }, \
{ CBMEM_ID_VBOOT_WORKBUF, "VBOOT WORK " }, \
{ CBMEM_ID_WIFI_CALIBRATION, "WIFI CLBR " },
#endif /* _CBMEM_ID_H_ */

414
board/coreboot/packages/cbmem/coreboot_tables.h
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#ifndef COREBOOT_TABLES_H
#define COREBOOT_TABLES_H
#include <stdint.h>
/* The coreboot table information is for conveying information
* from the firmware to the loaded OS image. Primarily this
* is expected to be information that cannot be discovered by
* other means, such as querying the hardware directly.
*
* All of the information should be Position Independent Data.
* That is it should be safe to relocated any of the information
* without it's meaning/correctness changing. For table that
* can reasonably be used on multiple architectures the data
* size should be fixed. This should ease the transition between
* 32 bit and 64 bit architectures etc.
*
* The completeness test for the information in this table is:
* - Can all of the hardware be detected?
* - Are the per motherboard constants available?
* - Is there enough to allow a kernel to run that was written before
* a particular motherboard is constructed? (Assuming the kernel
* has drivers for all of the hardware but it does not have
* assumptions on how the hardware is connected together).
*
* With this test it should be straight forward to determine if a
* table entry is required or not. This should remove much of the
* long term compatibility burden as table entries which are
* irrelevant or have been replaced by better alternatives may be
* dropped. Of course it is polite and expedite to include extra
* table entries and be backwards compatible, but it is not required.
*/
/* Since coreboot is usually compiled 32bit, gcc will align 64bit
* types to 32bit boundaries. If the coreboot table is dumped on a
* 64bit system, a uint64_t would be aligned to 64bit boundaries,
* breaking the table format.
*
* lb_uint64 will keep 64bit coreboot table values aligned to 32bit
* to ensure compatibility. They can be accessed with the two functions
* below: unpack_lb64() and pack_lb64()
*
* See also: util/lbtdump/lbtdump.c
*/
struct lb_uint64 {
uint32_t lo;
uint32_t hi;
};
static inline uint64_t unpack_lb64(struct lb_uint64 value)
{
uint64_t result;
result = value.hi;
result = (result << 32) + value.lo;
return result;
}
static inline struct lb_uint64 pack_lb64(uint64_t value)
{
struct lb_uint64 result;
result.lo = (value >> 0) & 0xffffffff;
result.hi = (value >> 32) & 0xffffffff;
return result;
}
struct lb_header
{
uint8_t signature[4]; /* LBIO */
uint32_t header_bytes;
uint32_t header_checksum;
uint32_t table_bytes;
uint32_t table_checksum;
uint32_t table_entries;
};
/* Every entry in the boot environment list will correspond to a boot
* info record. Encoding both type and size. The type is obviously
* so you can tell what it is. The size allows you to skip that
* boot environment record if you don't know what it is. This allows
* forward compatibility with records not yet defined.
*/
struct lb_record {
uint32_t tag; /* tag ID */
uint32_t size; /* size of record (in bytes) */
};
#define LB_TAG_UNUSED 0x0000
#define LB_TAG_MEMORY 0x0001
struct lb_memory_range {
struct lb_uint64 start;
struct lb_uint64 size;
uint32_t type;
#define LB_MEM_RAM 1 /* Memory anyone can use */
#define LB_MEM_RESERVED 2 /* Don't use this memory region */
#define LB_MEM_ACPI 3 /* ACPI Tables */
#define LB_MEM_NVS 4 /* ACPI NVS Memory */
#define LB_MEM_UNUSABLE 5 /* Unusable address space */
#define LB_MEM_VENDOR_RSVD 6 /* Vendor Reserved */
#define LB_MEM_TABLE 16 /* Ram configuration tables are kept in */
};
struct lb_memory {
uint32_t tag;
uint32_t size;
struct lb_memory_range map[0];
};
#define LB_TAG_HWRPB 0x0002
struct lb_hwrpb {
uint32_t tag;
uint32_t size;
uint64_t hwrpb;
};
#define LB_TAG_MAINBOARD 0x0003
struct lb_mainboard {
uint32_t tag;
uint32_t size;
uint8_t vendor_idx;
uint8_t part_number_idx;
uint8_t strings[0];
};
#define LB_TAG_VERSION 0x0004
#define LB_TAG_EXTRA_VERSION 0x0005
#define LB_TAG_BUILD 0x0006
#define LB_TAG_COMPILE_TIME 0x0007
#define LB_TAG_COMPILE_BY 0x0008
#define LB_TAG_COMPILE_HOST 0x0009
#define LB_TAG_COMPILE_DOMAIN 0x000a
#define LB_TAG_COMPILER 0x000b
#define LB_TAG_LINKER 0x000c
#define LB_TAG_ASSEMBLER 0x000d
struct lb_string {
uint32_t tag;
uint32_t size;
uint8_t string[0];
};
#define LB_TAG_VERSION_TIMESTAMP 0x0026
struct lb_timestamp {
uint32_t tag;
uint32_t size;
uint32_t timestamp;
};
/* 0xe is taken by v3 */
#define LB_TAG_SERIAL 0x000f
struct lb_serial {
uint32_t tag;
uint32_t size;
#define LB_SERIAL_TYPE_IO_MAPPED 1
#define LB_SERIAL_TYPE_MEMORY_MAPPED 2
uint32_t type;
uint32_t baseaddr;
uint32_t baud;
uint32_t regwidth;
};
#define LB_TAG_CONSOLE 0x0010
struct lb_console {
uint32_t tag;
uint32_t size;
uint16_t type;
};
#define LB_TAG_CONSOLE_SERIAL8250 0
#define LB_TAG_CONSOLE_VGA 1 // OBSOLETE
#define LB_TAG_CONSOLE_BTEXT 2 // OBSOLETE
#define LB_TAG_CONSOLE_LOGBUF 3 // OBSOLETE
#define LB_TAG_CONSOLE_SROM 4 // OBSOLETE
#define LB_TAG_CONSOLE_EHCI 5
#define LB_TAG_CONSOLE_SERIAL8250MEM 6
#define LB_TAG_FORWARD 0x0011
struct lb_forward {
uint32_t tag;
uint32_t size;
uint64_t forward;
};
#define LB_TAG_FRAMEBUFFER 0x0012
struct lb_framebuffer {
uint32_t tag;
uint32_t size;
uint64_t physical_address;
uint32_t x_resolution;
uint32_t y_resolution;
uint32_t bytes_per_line;
uint8_t bits_per_pixel;
uint8_t red_mask_pos;
uint8_t red_mask_size;
uint8_t green_mask_pos;
uint8_t green_mask_size;
uint8_t blue_mask_pos;
uint8_t blue_mask_size;
uint8_t reserved_mask_pos;
uint8_t reserved_mask_size;
};
#define LB_TAG_GPIO 0x0013
struct lb_gpio {
uint32_t port;
uint32_t polarity;
#define ACTIVE_LOW 0
#define ACTIVE_HIGH 1
uint32_t value;
#define GPIO_MAX_NAME_LENGTH 16
uint8_t name[GPIO_MAX_NAME_LENGTH];
};
struct lb_gpios {
uint32_t tag;
uint32_t size;
uint32_t count;
struct lb_gpio gpios[0];
};
#define LB_TAG_VDAT 0x0015
#define LB_TAG_VBNV 0x0019
#define LB_TAB_VBOOT_HANDOFF 0x0020
#define LB_TAB_DMA 0x0022
#define LB_TAG_RAM_OOPS 0x0023
#define LB_TAG_MTC 0x002b
struct lb_range {
uint32_t tag;
uint32_t size;
uint64_t range_start;
uint32_t range_size;
};
void lb_ramoops(struct lb_header *header);
#define LB_TAG_TIMESTAMPS 0x0016
#define LB_TAG_CBMEM_CONSOLE 0x0017
#define LB_TAG_MRC_CACHE 0x0018
#define LB_TAG_ACPI_GNVS 0x0024
#define LB_TAG_WIFI_CALIBRATION 0x0027
struct lb_cbmem_ref {
uint32_t tag;
uint32_t size;
uint64_t cbmem_addr;
};
#define LB_TAG_X86_ROM_MTRR 0x0021
struct lb_x86_rom_mtrr {
uint32_t tag;
uint32_t size;
/* The variable range MTRR index covering the ROM. */
uint32_t index;
};
#define LB_TAG_BOARD_ID 0x0025
struct lb_board_id {
uint32_t tag;
uint32_t size;
/* Board ID as retrieved from the board revision GPIOs. */
uint32_t board_id;
};
#define LB_TAG_MAC_ADDRS 0x0026
struct mac_address {
uint8_t mac_addr[6];
uint8_t pad[2]; /* Pad it to 8 bytes to keep it simple. */
};
struct lb_macs {
uint32_t tag;
uint32_t size;
uint32_t count;
struct mac_address mac_addrs[0];
};
#define LB_TAG_RAM_CODE 0x0028
struct lb_ram_code {
uint32_t tag;
uint32_t size;
uint32_t ram_code;
};
#define LB_TAG_SPI_FLASH 0x0029
struct lb_spi_flash {
uint32_t tag;
uint32_t size;
uint32_t flash_size;
uint32_t sector_size;
uint32_t erase_cmd;
};
#define LB_TAG_BOOT_MEDIA_PARAMS 0x0030
struct lb_boot_media_params {
uint32_t tag;
uint32_t size;
/* offsets are relative to start of boot media */
uint64_t fmap_offset;
uint64_t cbfs_offset;
uint64_t cbfs_size;
uint64_t boot_media_size;
};
#define LB_TAG_SERIALNO 0x002a
#define MAX_SERIALNO_LENGTH 32
/* The following structures are for the cmos definitions table */
#define LB_TAG_CMOS_OPTION_TABLE 200
/* cmos header record */
struct cmos_option_table {
uint32_t tag; /* CMOS definitions table type */
uint32_t size; /* size of the entire table */
uint32_t header_length; /* length of header */
};
/* cmos entry record
This record is variable length. The name field may be
shorter than CMOS_MAX_NAME_LENGTH. The entry may start
anywhere in the byte, but can not span bytes unless it
starts at the beginning of the byte and the length is
fills complete bytes.
*/
#define LB_TAG_OPTION 201
struct cmos_entries {
uint32_t tag; /* entry type */
uint32_t size; /* length of this record */
uint32_t bit; /* starting bit from start of image */
uint32_t length; /* length of field in bits */
uint32_t config; /* e=enumeration, h=hex, r=reserved */
uint32_t config_id; /* a number linking to an enumeration record */
#define CMOS_MAX_NAME_LENGTH 32
uint8_t name[CMOS_MAX_NAME_LENGTH]; /* name of entry in ascii,
variable length int aligned */
};
/* cmos enumerations record
This record is variable length. The text field may be
shorter than CMOS_MAX_TEXT_LENGTH.
*/
#define LB_TAG_OPTION_ENUM 202
struct cmos_enums {
uint32_t tag; /* enumeration type */
uint32_t size; /* length of this record */
uint32_t config_id; /* a number identifying the config id */
uint32_t value; /* the value associated with the text */
#define CMOS_MAX_TEXT_LENGTH 32
uint8_t text[CMOS_MAX_TEXT_LENGTH]; /* enum description in ascii,
variable length int aligned */
};
/* cmos defaults record
This record contains default settings for the cmos ram.
*/
#define LB_TAG_OPTION_DEFAULTS 203
struct cmos_defaults {
uint32_t tag; /* default type */
uint32_t size; /* length of this record */
uint32_t name_length; /* length of the following name field */
uint8_t name[CMOS_MAX_NAME_LENGTH]; /* name identifying the default */
#define CMOS_IMAGE_BUFFER_SIZE 256
uint8_t default_set[CMOS_IMAGE_BUFFER_SIZE]; /* default settings */
};
#define LB_TAG_OPTION_CHECKSUM 204
struct cmos_checksum {
uint32_t tag;
uint32_t size;
/* In practice everything is byte aligned, but things are measured
* in bits to be consistent.
*/
uint32_t range_start; /* First bit that is checksummed (byte aligned) */
uint32_t range_end; /* Last bit that is checksummed (byte aligned) */
uint32_t location; /* First bit of the checksum (byte aligned) */
uint32_t type; /* Checksum algorithm that is used */
#define CHECKSUM_NONE 0
#define CHECKSUM_PCBIOS 1
};
/* function prototypes for building the coreboot table */
unsigned long write_coreboot_table(
unsigned long low_table_start, unsigned long low_table_end,
unsigned long rom_table_start, unsigned long rom_table_end);
void fill_lb_gpios(struct lb_gpios *gpios);
void fill_lb_gpio(struct lb_gpio *gpio, int num,
int polarity, const char *name, int value);
void uart_fill_lb(void *data);
void lb_add_serial(struct lb_serial *serial, void *data);
void lb_add_console(uint16_t consoletype, void *data);
/* Define this in mainboard.c to add board-specific table entries. */
void lb_board(struct lb_header *header);
/*
* Function to retrieve MAC address(es) from the VPD and store them in the
* coreboot table.
*/
void lb_table_add_macs_from_vpd(struct lb_header *header);
void lb_table_add_serialno_from_vpd(struct lb_header *header);
struct lb_record *lb_new_record(struct lb_header *header);
#endif /* COREBOOT_TABLES_H */

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board/coreboot/packages/cbmem/timestamp.h
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc.
*/
#ifndef __TIMESTAMP_H__
#define __TIMESTAMP_H__
#include <stdint.h>
struct timestamp_entry {
uint32_t entry_id;
uint64_t entry_stamp;
} __attribute__((packed));
struct timestamp_table {
uint64_t base_time;
uint16_t max_entries;
uint16_t tick_freq_mhz;
uint32_t num_entries;
struct timestamp_entry entries[0]; /* Variable number of entries */
} __attribute__((packed));
enum timestamp_id {
TS_START_ROMSTAGE = 1,
TS_BEFORE_INITRAM = 2,
TS_AFTER_INITRAM = 3,
TS_END_ROMSTAGE = 4,
TS_START_VBOOT = 5,
TS_END_VBOOT = 6,
TS_START_COPYRAM = 8,
TS_END_COPYRAM = 9,
TS_START_RAMSTAGE = 10,
TS_START_BOOTBLOCK = 11,
TS_END_BOOTBLOCK = 12,
TS_START_COPYROM = 13,
TS_END_COPYROM = 14,
TS_START_ULZMA = 15,
TS_END_ULZMA = 16,
TS_DEVICE_ENUMERATE = 30,
TS_DEVICE_CONFIGURE = 40,
TS_DEVICE_ENABLE = 50,
TS_DEVICE_INITIALIZE = 60,
TS_DEVICE_DONE = 70,
TS_CBMEM_POST = 75,
TS_WRITE_TABLES = 80,
TS_LOAD_PAYLOAD = 90,
TS_ACPI_WAKE_JUMP = 98,
TS_SELFBOOT_JUMP = 99,
/* 500+ reserved for vendorcode extensions (500-600: google/chromeos) */
TS_START_COPYVER = 501,
TS_END_COPYVER = 502,
TS_START_TPMINIT = 503,
TS_END_TPMINIT = 504,
TS_START_VERIFY_SLOT = 505,
TS_END_VERIFY_SLOT = 506,
TS_START_HASH_BODY = 507,
TS_DONE_LOADING = 508,
TS_DONE_HASHING = 509,
TS_END_HASH_BODY = 510,
/* 950+ reserved for vendorcode extensions (950-999: intel/fsp) */
TS_FSP_MEMORY_INIT_START = 950,
TS_FSP_MEMORY_INIT_END = 951,
TS_FSP_TEMP_RAM_EXIT_START = 952,
TS_FSP_TEMP_RAM_EXIT_END = 953,
TS_FSP_SILICON_INIT_START = 954,
TS_FSP_SILICON_INIT_END = 955,
TS_FSP_BEFORE_ENUMERATE = 956,
TS_FSP_AFTER_ENUMERATE = 957,
TS_FSP_BEFORE_FINALIZE = 958,
TS_FSP_AFTER_FINALIZE = 959,
/* 1000+ reserved for payloads (1000-1200: ChromeOS depthcharge) */
};
#if CONFIG_COLLECT_TIMESTAMPS && (CONFIG_EARLY_CBMEM_INIT || !defined(__PRE_RAM__))
/*
* timestamp_init() needs to be called once for each of these cases:
* 1. __PRE_RAM__ (bootblock, romstage, verstage, etc) and
* 2. !__PRE_RAM__ (ramstage)
* The latter is taken care of by the generic coreboot infrastructure so
* it's up to the chipset/arch to call timestamp_init() in *one* of
* the __PRE_RAM__ stages. If multiple calls are made timestamps will be lost.
*/
void timestamp_init(uint64_t base);
/*
* Add a new timestamp. Depending on cbmem is available or not, this timestamp
* will be stored to cbmem / timestamp cache.
*/
void timestamp_add(enum timestamp_id id, uint64_t ts_time);
/* Calls timestamp_add with current timestamp. */
void timestamp_add_now(enum timestamp_id id);
#else
#define timestamp_init(base)
#define timestamp_add(id, time)
#define timestamp_add_now(id)
#endif
/* Implemented by the architecture code */
uint64_t timestamp_get(void);
uint64_t get_initial_timestamp(void);
/* Returns timestamp tick frequency in MHz. */
int timestamp_tick_freq_mhz(void);
#endif

1
configs/coreboot_defconfig
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@ -58,6 +58,7 @@ BR2_TARGET_ROOTFS_CPIO_XZ=y
# BR2_TARGET_ROOTFS_TAR is not set
BR2_PACKAGE_CONNECTPROXY=y
BR2_PACKAGE_CBFSTOOL=y
BR2_PACKAGE_CBMEM=y
BR2_PACKAGE_IFDTOOL=y
BR2_PACKAGE_NVRAMTOOL=y
BR2_DEFCONFIG="$(BR2_EXTERNAL)/configs/coreboot_defconfig"

1
package/Config.in
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@ -5,6 +5,7 @@ endmenu
menu "Coreboot"
source "$BR2_EXTERNAL/package/coreboot/cbfstool/Config.in"
source "$BR2_EXTERNAL/package/coreboot/cbmem/Config.in"
source "$BR2_EXTERNAL/package/coreboot/ifdtool/Config.in"
source "$BR2_EXTERNAL/package/coreboot/nvramtool/Config.in"
endmenu

7
package/coreboot/cbmem/Config.in
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@ -0,0 +1,7 @@
config BR2_PACKAGE_CBMEM
bool "cbmem"
depends on BR2_i386 || BR2_x86_64
help
cbmem is a tool for reading coreboot log dumps in memory
http://www.coreboot.org/

22
package/coreboot/cbmem/cbmem.mk
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@ -0,0 +1,22 @@
################################################################################
#
# cbmem
#
################################################################################
CBMEM_VERSION = 1.1
CBMEM_SITE = $(BR2_EXTERNAL)/board/coreboot/packages/cbmem
CBMEM_SITE_METHOD = local
CBMEM_LICENSE = GPLv2
CBMEM_LICENSE_FILES = COPYING
CBMEM_CFLAGS = $(TARGET_CFLAGS) -I$(@D)
define CBMEM_BUILD_CMDS
$(MAKE) $(TARGET_CONFIGURE_OPTS) CC="$(TARGET_CC)" -C "$(@D)"
endef
define CBMEM_INSTALL_TARGET_CMDS
$(INSTALL) -m 0755 -D $(@D)/cbmem $(TARGET_DIR)/usr/sbin/cbmem
endef
$(eval $(generic-package))
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