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122 lines
3.5 KiB
122 lines
3.5 KiB
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc.
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*/
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#ifndef __TIMESTAMP_H__
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#define __TIMESTAMP_H__
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#include <stdint.h>
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struct timestamp_entry {
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uint32_t entry_id;
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uint64_t entry_stamp;
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} __attribute__((packed));
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struct timestamp_table {
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uint64_t base_time;
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uint16_t max_entries;
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uint16_t tick_freq_mhz;
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uint32_t num_entries;
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struct timestamp_entry entries[0]; /* Variable number of entries */
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} __attribute__((packed));
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enum timestamp_id {
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TS_START_ROMSTAGE = 1,
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TS_BEFORE_INITRAM = 2,
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TS_AFTER_INITRAM = 3,
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TS_END_ROMSTAGE = 4,
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TS_START_VBOOT = 5,
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TS_END_VBOOT = 6,
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TS_START_COPYRAM = 8,
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TS_END_COPYRAM = 9,
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TS_START_RAMSTAGE = 10,
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TS_START_BOOTBLOCK = 11,
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TS_END_BOOTBLOCK = 12,
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TS_START_COPYROM = 13,
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TS_END_COPYROM = 14,
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TS_START_ULZMA = 15,
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TS_END_ULZMA = 16,
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TS_DEVICE_ENUMERATE = 30,
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TS_DEVICE_CONFIGURE = 40,
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TS_DEVICE_ENABLE = 50,
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TS_DEVICE_INITIALIZE = 60,
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TS_DEVICE_DONE = 70,
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TS_CBMEM_POST = 75,
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TS_WRITE_TABLES = 80,
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TS_LOAD_PAYLOAD = 90,
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TS_ACPI_WAKE_JUMP = 98,
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TS_SELFBOOT_JUMP = 99,
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/* 500+ reserved for vendorcode extensions (500-600: google/chromeos) */
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TS_START_COPYVER = 501,
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TS_END_COPYVER = 502,
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TS_START_TPMINIT = 503,
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TS_END_TPMINIT = 504,
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TS_START_VERIFY_SLOT = 505,
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TS_END_VERIFY_SLOT = 506,
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TS_START_HASH_BODY = 507,
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TS_DONE_LOADING = 508,
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TS_DONE_HASHING = 509,
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TS_END_HASH_BODY = 510,
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/* 950+ reserved for vendorcode extensions (950-999: intel/fsp) */
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TS_FSP_MEMORY_INIT_START = 950,
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TS_FSP_MEMORY_INIT_END = 951,
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TS_FSP_TEMP_RAM_EXIT_START = 952,
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TS_FSP_TEMP_RAM_EXIT_END = 953,
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TS_FSP_SILICON_INIT_START = 954,
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TS_FSP_SILICON_INIT_END = 955,
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TS_FSP_BEFORE_ENUMERATE = 956,
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TS_FSP_AFTER_ENUMERATE = 957,
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TS_FSP_BEFORE_FINALIZE = 958,
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TS_FSP_AFTER_FINALIZE = 959,
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/* 1000+ reserved for payloads (1000-1200: ChromeOS depthcharge) */
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};
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#if CONFIG_COLLECT_TIMESTAMPS && (CONFIG_EARLY_CBMEM_INIT || !defined(__PRE_RAM__))
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/*
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* timestamp_init() needs to be called once for each of these cases:
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* 1. __PRE_RAM__ (bootblock, romstage, verstage, etc) and
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* 2. !__PRE_RAM__ (ramstage)
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* The latter is taken care of by the generic coreboot infrastructure so
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* it's up to the chipset/arch to call timestamp_init() in *one* of
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* the __PRE_RAM__ stages. If multiple calls are made timestamps will be lost.
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*/
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void timestamp_init(uint64_t base);
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/*
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* Add a new timestamp. Depending on cbmem is available or not, this timestamp
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* will be stored to cbmem / timestamp cache.
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*/
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void timestamp_add(enum timestamp_id id, uint64_t ts_time);
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/* Calls timestamp_add with current timestamp. */
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void timestamp_add_now(enum timestamp_id id);
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#else
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#define timestamp_init(base)
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#define timestamp_add(id, time)
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#define timestamp_add_now(id)
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#endif
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/* Implemented by the architecture code */
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uint64_t timestamp_get(void);
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uint64_t get_initial_timestamp(void);
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/* Returns timestamp tick frequency in MHz. */
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int timestamp_tick_freq_mhz(void);
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#endif
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