diff --git a/branches/follower/wiz810mj/src/demo/WizDemo1/WizDemo1.pde b/branches/follower/wiz810mj/src/demo/WizDemo1/WizDemo1.pde
index 6a70cb8..7fa525d 100644
--- a/branches/follower/wiz810mj/src/demo/WizDemo1/WizDemo1.pde
+++ b/branches/follower/wiz810mj/src/demo/WizDemo1/WizDemo1.pde
@@ -64,16 +64,18 @@ void configureSPI() {
   
   digitalWrite(PIN_SLAVE_SELECT, HIGH); // Disable slave
   
-  //    Configure SPI Control Register (SPCR) (All values initially 0)
-  //     Bit  Description
-  //       7  SPI Interrupt Enable    -- disable  (SPIE --> 0)
-  //       6  SPI Enable              -- enable   (SPE  --> 1)
-  //       5  Data Order              -- MSB 1st  (DORD --> 0) (Slave specific)
-  //       4  Master/Slave Select     -- master   (MSTR --> 1)
-  //       3  Clock Polarity          --          (CPOL --> 0) (Slave specific) ("Mode")
-  //       2  Clock Phase             --          (CPHA --> 0) (Slave specific)
-  //       1  SPI Clock Rate Select 1 -- }        (SPR1 --> 0) 
-  //       0  SPI Clock Rate Select 0 -- } fOSC/4 (SPR0 --> 0) ("Fastest" but see SPI2X in SPSR)
+  /*
+     Configure SPI Control Register (SPCR) (All values initially 0)
+      Bit  Description
+        7  SPI Interrupt Enable    -- disable  (SPIE --> 0)
+        6  SPI Enable              -- enable   (SPE  --> 1)
+        5  Data Order              -- MSB 1st  (DORD --> 0) (Slave specific)
+        4  Master/Slave Select     -- master   (MSTR --> 1)
+        3  Clock Polarity          --          (CPOL --> 0) (Slave specific) ("Mode")
+        2  Clock Phase             --          (CPHA --> 0) (Slave specific)
+        1  SPI Clock Rate Select 1 -- }        (SPR1 --> 0) 
+        0  SPI Clock Rate Select 0 -- } fOSC/4 (SPR0 --> 0) ("Fastest" but see SPI2X in SPSR)
+  */
   SPCR = (1<<SPE)| (1<<MSTR);
 
   // Clear previous data and status (TODO: Determine if necessary/better way.)